1. Field of the Invention
The present invention relates to electrically erasable, programmable, read only memory (EEPROM) devices and, in particular, to a flash EEPROM memory system suitable for low voltage operation and a method of controlling such memory.
2. Background Art
Programmable, electrically erasable, read only memories are non-volatile field effect devices which utilize a floating gate structure. Standard EEPROMs, or electrically erasable, programmable memories, include memories wherein the cells may be individually programmed and erased. However, this type of EEPROM requires a wide range of voltages for programming, reading and erasing and the cells are relatively large.
Flash EEPROMs have been developed which have a smaller cell size then standard EEPROM. Flash EEPROMs have cells that cannot be individually erased, but are erased either in bulk or by sector. Referring now to the drawings, FIG. 1A depicts a conventional N channel flash EEPROM memory cell 18, commonly referred to as the Intel ETOX cell or simply the ETOX cell. The cell includes a graded N type source region 20 diffused into a P type substrate 22. An N type drain region 24 is also diffused into the substrate 22 so as to define a channel region 22a between the source and drain regions. The source region 20 is formed more deeply into the substrate 22 than is the drain region 24.
A polysilicon floating gate 26 is disposed above the channel 22a and is separated from the channel by a thin (about 100 .ANG.) gate oxide 28. A portion of floating gate 26 extends over the graded source region 20. A polysilicon control gate 30 is disposed above the floating gate 26 and is separated from the floating gate by an interpoly dielectric layer 32.
FIGS. 1A-1C show typical conditions for programming, reading and erasing the cell 18, assuming that the primary supply voltage Vcc is +5 volts.
As shown in FIG. 1A, the ETOX flash cell is programmed by applying a programming voltage +Vpp (typically +6 to +8 volts) to the drain region 24 and a higher voltage Vgg (typically +10 to +13 volts) to the control electrode. The source region is grounded (Vss). Voltage +Vpp is usually supplied from an external source and voltage Vgg is usually provided by way of a charge pump type circuit. Alternatively, both Vpp and Vgg can be provided by a charge pump circuit, with only primary voltage Vcc being provided by an external source or supply.
The ETOX cell is programmed in the conventional standard EEPROM manner. Electrons exit the source 20 and are accelerated across the channel 22a towards the drain region 24. As the electrons approach the drain, the positive charge on the control gate 32 results in avalanche or hot electron injection near the drain 24 through the gate oxide and into the polysilicon floating gate 26. As will be explained, the presence of electrons on the floating gate 26 of a programmed cell produces characteristics which differ from an unprogrammed cell.
The conventional ETOX cell is read in the manner shown in FIG. 1B. The source region 20 is grounded (Vss) and an intermediate voltage +Vf (typically +1 to +1.5 volts) is applied to the drain region 24. Voltage +Vcc is applied to the control gate 30. In the case where the cell had been previously programmed, the negative charge present on the floating gate will tend to prevent the positive voltage on the control electrode 32 from inverting the channel. Thus, the negative charge on the gate effectively increases the threshold voltage of the cell so that the cell will not be rendered conductive by the voltage +Vcc applied to the control gate 30. Accordingly, no current flow will take place through the cell other than some amount of leakage current.
In the event the cell of FIG. 1B was not previously programmed, the threshold voltage of the cell will be sufficiently low such that the cell will be rendered conductive by voltage +Vcc. This will result in current flow through the cell which will be detected by the sense amplifier.
The ETOX cell is erased in the manner depicted in FIG. 1C. The drain region 24 is left open (floating) and control gate 30 is grounded (Vss).
Positive voltage +Vee, typically ranging from +11 to +13 volts, is applied to the source region 20 which results in electrons being drawn off floating gate 26 through the thin gate oxide 28 to the graded source region 20. This occurs in the region of the graded source which underlies the floating gate 26. The mechanism for such removal of electrons is known as Fowler-Nordheim tunneling. The graded source 20 provides a smooth curvature which increases the gate-aided junction break down voltage. Thus, the asymmetrical drain/source configuration, including the graded source and the section of the source underlying the floating gate 26 enhances the Fowler-Nordheim tunneling mechanism used in the erase process.
FIG. 2 shows a conventional memory array 32 comprised of flash cells 18 arranged in rows and columns. The source regions 20 of each of the cells is connected to a common source line S. Note that cells located in a particular column are arranged in pairs, such as the pair comprising cells 18A and 18B, with each cell 18 of a pair having a reversed orientation so that the source regions are adjacent to one another. The drain region 24 of each cell 18 located in a particular column is connected to a common bit line BLN. Further, the control electrode 30 of each cell located in a particular row is connected to a common word line WLN.
The memory system includes the memory array 32 and associated circuitry (not depicted) for decoding read/write addresses and for applying the appropriate voltages necessary for carrying out the program, read and erase steps. In addition, the associated circuitry includes sense amplifiers and related components for reading the array.
Operation of the conventional memory system is best described by way of example. If cell 18A is to be programmed, positive voltage +Vgg is applied to the selected word line WL1. The deselected word lines WL0, WL2, WL3 and WLN are all grounded. In addition, positive voltage +Vpp is applied to the selected bit line BL2, with the deselected bit lines all being grounded (Vss). Cell 18A will be programmed as previously described in connection with FIG. 1A. The deselected cells in the same column, such as cell 18B, will not be programmed because of the deselected word lines, including line WL0, are grounded. Similarly, the deselected cells in the same row, such as cell 18C, will not be programmed because the deselected bit lines, including line BL1, are grounded (Vss).
Reading is carried out by applying voltage +Vcc to the selected word line, such as line WL1 if cell 18A is to be read. The deselected word lines, WL0, WL2, WL3 and WLN, are all grounded as is the common source line S. Further, the deselected bit lines BL0, BL1 and BAN are all grounded (Vss) and the selected bit line BL1 will be connected to positive voltage +Vf. The deselected cells will not be rendered conductive. For cells in the same column, such as cell 18B, the grounded word line WL0 will maintain the cell in a non-conductive condition. For deselected cells in the same row, such as cell 18C, such cells will remain non-conductive since the associated bit lines are grounded (Vss).
Although not depicted, the memory system includes a sense amplifier and load associated with each column for sensing current flow through any of the cells located in the column. The load, which is typically an MOS transistor, is connected between the bit line and voltage +Vcc and functions as a voltage divider so as to produce voltage +Vf when no current is flowing through the bit line. In the event the selected cell 18A is in the unprogrammed or erased state, the cell will conduct current so that current flow will take place between bit line BL1 and the common source line S. The current will flow through the associated load will cause the voltage on the bit line to drop from the quiescent value of +Vf to a lower value. In the event the cell has been programmed, the cell will remain non-conductive and the voltage on the bit line will remain unchanged except for the changes attributable to leakage current. The output of the sense amplifier will thus reflect the programmed state of the selected cell.
The erase sequence is carried out by connecting the common source line S to positive voltage +Vee, grounding (Vss) all of the word lines WLN and floating all of the bit lines BAN. This causes all of the cells 18 of the array to be erased.
There has been a tendency to reduce the magnitude of the supply voltage so as to permit battery operation. By way of example, voltage +Vcc can be reduced from a typical value of +5 volts to +3 volts. The other voltages, including voltages +Vp and +Vgg, are then typically generated using on-chip charge pump circuitry.
One disadvantage of low voltage operation is that a low value of +Vcc results in a low cell current during a read operation (FIG. 1B). A low cell current results in slow access times since the amount of current available to charge and discharge the memory line capacitances is small. In order to increase the cell current, it would be possible to utilize an on-chip charge pump to generate a larger voltage +Vcc, but charge pumps increase the die size and waste power. Further, since the voltage +Vcc applied to the control electrode must be rapidly switched on and off during successive read operations, the inherent slow speed of charge pumps greatly reduces the time required to read the memory. Since memory read operations are much more critical to overall speed of the memory as compared to program and erase operations, this is highly undesirable.
One approach to increasing cell current is to decrease the threshold voltage of the cell. However, this will result in large leakage currents in deselected cells despite the fact that a low voltage is applied to the control gate of such cells. In addition, there is a tendency to program cells having a low threshold voltage when such cells are read. This phenomena, known as program disturb, is not desirable.
The present invention overcomes the above-noted shortcomings of conventional memory systems. Low voltage operation is achieved without the use of charge pumps to supply voltage +Vcc. Further, cell current is sufficient so as to maintain high speed memory read operations while maintaining immunity to leakage current from deselected cells and while avoiding program disturb. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.